The present invention relates to a transistor and a method of fabricating the same, and more particularly to a transistor to be used in high integration and low power LSI on an SOI substrate.
A conventional and typical body driven SOI-MOS field effect transistor will be described with reference to FIG. 1 which is a fragmentary cross sectional elevation view illustrative of the conventional and typical body driven SOI-MOS field effect transistor. A buried oxide film 102 is formed over a silicon substrate 101. An SOI layer 103 is formed over the buried oxide film 102. A gate oxide film 104 is formed on the SOI layer 103. A gate electrode 106 is formed on the gate oxide film 104. The SOI layer 103 comprises source/drain regions 105 sandwiching a body region 108 which is positioned under the gate oxide film 104. The body region 108 is introduced with a second conductivity type impurity at 1.times.10.sup.17 cm.sup.-3 through 1.times.10.sup.18 cm.sup.-3. If the gate voltage is applied to the gate, the body region 108 is divided into a neutral region 107 and a depletion region 109. A channel is formed on a top interface of the body region 108 in contact with the gate oxide film 104. A gate-channel capacitance Ccb and a channel-substrate capacitance exist.
Another SOI-MOS field effect transistor was reported by F. Assaderaghi et al. in IEDM 94, Technical Digest, p. 809. This conventional transistor has a structure as illustrated in FIG. 2 wherein an input signal is inputted into not only the gate but also the SOI layer by connecting the gate and the SOI layer by an interconnection H for high speed operations under low voltage.
The conventional SOI-MOS field effect transistor has the following two issues to be solved.
The first issue is concerned with the short channel effects of the SOI-MOS field effect transistors.
At first, relationships of the short channel effects to the thickness of the gate oxide film will be described. As the field effect transistor is scaled down and a channel length is shortened, the short channel effects deteriorate the performances of the transistor because the threshold voltage is dropped or the abruptness of the subthreshold is deteriorated due to influence of two dimensional electric fields from the source/drain regions.
In order to solve this problem, it was proposed to reduce the thickness of the gate oxide film for increasing a gate-channel capacitance Ccg with a coupling capacitance between the gate and channel. As a result, the controllability to the channel by the gate electrode is increased to thereby suppress the short channel effects.
The reduction in thickness of the gate oxide film raises the problems with difficulty in forming an extremely thin gate oxide film and in addition another difficulty in securing the quality of the gate oxide film in view of insulation performance and reliability over time.
In order to scale down the transistor, it is required to increase the gate-channel capacitance without reduction in thickness of the gate oxide film.
Subsequently, dependency of the short channel effects upon the impurity concentration will be described.
In order to suppress the short channel effects, it was proposed to increase the impurity concentration of the substrate. As illustrated in FIG. 3, if the impurity concentration is increased, the width of the depletion region 109 is made narrow and the neutral region 107 approaches the source/drain regions 105. For those reasons, the electric field from the source/drain regions increases in component to be terminated by the neutral region 107 whereby the deterioration in performance of the transistor due to the two-dimensional electric field from the source/drain regions 105 can be suppressed.
On the other hand, the threshold voltage of the transistor also depends upon the impurity concentration of the substrate. As illustrated in FIG. 3, if the impurity concentration of the substrate is increased, then the threshold voltage is varied. The setting of the threshold voltage and the suppression of the short channel effects are harmfully dependent upon and influenced by each other. It is difficult for the conventional transistor to control the impurity concentration of the substrate and the threshold voltage independently.
The controllability YC to the channel is high when the gate-channel capacitance Ccg is large whilst the channel-substrate capacitance Ccb is small. With reference back to FIG. 1, the channel potential is decided by a potential division by two capacitances connected in series, for example, the gate-channel capacitance Ccg and the channel-substrate capacitance Ccb. If a ratio of the gate-channel capacitance Ccg to the channel-substrate capacitance Ccb is increased, then a difference between the channel potential and the gate potential is decreased, whereby a responsibility of the channel potential to the gate potential is improved and thus the controllability to the channel by the gate is improved.
In the normal and conventional field effect transistors, if the impurity concentration of the substrate is increased for suppressing the short channel effects, then the gate-channel capacitance Ccg remains unchanged but the channel-substrate capacitance Ccb is increased whereby controllability to the channel by the gate is deteriorated and also S-factor is deteriorated. S-factor means a variation in gate voltage necessary for changing the subthreshold voltage by one order.
In view of the scaling down the transistor, it is required to increase the impurity concentration of the substrate without providing any influence to the threshold voltage and the channel-substrate capacitance.
The above description may be applied to the transistor illustrated in FIG. 2.
The subsequent descriptions will focus on the second issue concerning the substrate floating effect of the SOIMOSFET. The insulation layer separates the substrate and the SOI semiconductor layer of a first conductivity type in the SOI structure, for which reason second conductivity type carriers are prevented by the buried oxide film from flowing between the substrate and the SOI semiconductor layer. Since the body driven SOIMOSFET is operated by a low voltage, if bias conditions are changed, the neutral region varies in width thereby causing excess carriers or holes or resulting in lack of holes. Notwithstanding, the excess carriers are prevented by the buried oxide film from exhaustion to the substrate or supply of holes to the SOI layer. This may cause transient abnormal operations of the transistor. Further, incidence of alpharay in the channel direction causes atomic ionization of the semiconductor thereby generating the second conductivity type carrier in the SOI layer. Notwithstanding, the second conductivity type carrier is prevented by the buried oxide layer from exhaustion to the substrate.
For the stable operations of the transistor, a structure allowing supply and exhaustion of holes is needed.
In the above circumstances, it has been required to develop a novel body driven SOI-MOS field effect transistors free from the above problems.